Везде
Temperature dependences of the breakdown voltage of a high-voltage LDMOS transistor
Table of contents
Annotation Estimate Publication content
References Comments
Share
QR
Metrics
Temperature dependences of the breakdown voltage of a high-voltage LDMOS transistor
Annotation
PII
S0544126924050098-1
Publication type
Article
Status
Published
Authors
N. V. Masalsky 
Affiliation: Federal State Institution Federal Scientific Center Scientific Research Institute of System Research of the Russian Academy of Sciences
Edition
Volume 53 Issue number 5
Pages
439-447
Abstract
The results of a study of the temperature dependences of the breakdown voltage of high-power nLDMOS transistors with a long drift region with topological norms of 0.5 microns are discussed. The main attention is focused on the effect of the mechanism of generation and passivation of traps at the Si/SiO2 interface in strong electric fields. The dependence of the breakdown voltage in the ambient temperature range from -60 °C to 300 °C has been experimentally and theoretically analyzed and the temperature range from 25 °C to 220 °C, where the breakdown voltage is almost constant, has been determined. The possibility of restoring the breakdown voltage level after a long period of rest is considered, which is a prerequisite for extending the life of the device.
Keywords
технология «кремний на изоляторе» мощный LDMOS температурная зависимость напряжения пробоя деградация горячих носителей моделирование тестирование
Acknowledgment
The publication was carried out within the framework of the state assignment of the Federal State Institution Federal Scientific Center of the Russian Academy of Sciences (Conducting Fundamental Scientific Research (47 GP)) on the topic "1023032900380-3-1.2.1 Fundamental and applied research in the field of lithographic limits of semiconductor technologies and physicochemical processes of etching 3D nanometer dielectric structures for the development of critical technologies for the production of electronic components. Research and construction of models and designs of microelectronic elements in an extended temperature range (from -60C to +300C). (FNEF-2024-0004)".
Received
24.02.2025
Number of purchasers
0
Views
21
Readers community rating
0.0 (0 votes)
Cite   Download pdf

References

1. International Technology Roadmap for Semiconductors (ITRS) Interconnect, 2020 Edition. [Online] Available: https://irds.ieee.org/editions/2020 (data access 12.02.2023).

2. de Jong M.J., Salm C., Schmitz J. Effect of Ambient on the Recovery of Hot-Carrier Degraded Devices // In Proceedings of the 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 28 April-30 May 2020. P. 1–6.

3. Chuang K.H., Bury E., Degraeve R., Kaczer B., Kallstenius T., Groeseneken G., Linten D., I. Verbauwhede I. A multi-bit/cell PUF using analog breakdown positions in CMOS // IEEE International Reliability Physics Symposium (IRPS). 2018. 11–15 March 2018. Burlingame, CA, USA. P. PCR.2.1–PCR.2.5.

4. Nanoelectronics: Devices, Circuits and Systems. Editor by Brajesh Kumar Kaushik. Elsevier. 2018.

5. Reggiani S., Barone G., Gnani E., Gnudi A., Baccarani G., Poli S., Wise R, Chuang M.Y., Tian W., Pendharkar S., Denison M. Characterization and modeling of high-voltage LDMOS transistors in book Hot carrier degradation semiconductor devices by ed T. Grasser, 2015, Springer Cham Heidelberg New York Dordrecht London. P. 309–340.

6. Liebmann L., Smith J., Chanemougame D., Gutwin P. CFET Design Options, Challenges, and Opportunities for 3D Integration. In Proceedings of the 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 13–15 December 2021. P. 3.1.1–3.1.4.

7. Stesmans A. Passivation of Pb0 and Pb1 interface defects in thermal (100) Si/SiO2 with molecular hydrogen // Applied Physics Letters. 1996. V. 68. № 15. P. 2076–2078.

8. Румянцев С.В., Новоселов А.С., Масальский Н.В. Исследование эффекта самонагревания в высоковольтных КНИ транзисторах с большой областью дрейфа. Микроэлектроника. 2022. T. 51. № 5. C. 377–385.

9. Lundstrom M., Guo J. Nanoscale Transistors: Device Physics, Modeling and Simulation. Springer: New York, 2006.

10. Tang T.W., Gan H. Two formulations of semiconductor transport equations based on spherical harmonic expansion of the Boltzmann transport equations // IEEE Trans. Elec. Dev. 2000. V. 47. P. 1726–1732.

11. McMahon W., Haggag A., Hess K. Reliability Scaling Issues for Nanoscale Devices // IEEE Trans. Nanotech., 2003. V. 2. № 1. P. 33–38.

12. Новоселов А.С., Масальский Н.В. Влияние деградации горячих носителей на характеристики высоковольтного КНИ транзистора с большой областью дрейфа // Микроэлектроника. 2023 T. 52. № 5. C. 423–430.

13. Ragnarsson. L.A., Lundgren P. Electrical characterization of Pb centers in (100) Si–SiO2 structures: the influence of surface potential on passivation during post metallization anneal // Journal of Applied Physics. 2000. V. 88. № 2. P. 938–942.

14. Federspiel X., Torrente G., Arfaoui W., Cacho F., Huard V. Temperature sense effect in HCI self-heating de convolution: application to 28nm FDSOI // IEEE International Reliability Physics Symposium (IRPS). 2016. P. XT-09–1–XT-09–4.

15. Hot-Carrier Degradation, ed. By T. Grasser, Springer, Wien, New York, 2015.

16. Brower K.L. Dissociation kinetics of hydrogen-passivated (111) Si-SiO2 interface defects // Physical Review B. 1990. V. 42. № 6. P. 3444–3454.

17. Brower K.L. Kinetics of H2 passivation of Pb centers at the (111) Si-SiO2 interface // Physical Review B. 1988. V. 38. № 14. P. 9657–9664.

18. Rashkeev S., Ventra M., Pantelides S. Hydrogen passivation and activation of oxygen complexes in silicon // Applied Physics Letters. 2001. V. 78. P. 1571–1573.

19. Grasser T. The capture/emission time map approach to the bias temperature instability. in Bias Temperature Instability for Devices and Circuits. Springer, 2014, P. 447–481.

20. Lee G.B., Kim C.K., Park J.Y., Bang T., Bae H., Kim S.Y., Ryu S.W., Choi Y.K. A novel technique for curing hot-carrier induced damage by utilizing the forward current of the PN-junction in a MOSFET // IEEE Electron Device Letters. 2017. V. 38. № 8. P. 1012–1014.

21. de Jong M. ., Salm C., Schmitz J. Towards understanding recovery of hot-carrier induced degradation. Microelectronics Reliability. 2018. V. 88. P. 147–151.

22. 22. Edwards A. H. Interaction of H and H2 with the silicon dangling orbital at the 〈111〉 Si/SiO2 interface // Physical Review B. 1991. V. 44. № 4. P. 1832–1838.

23. Guerin C., Huard V., Bravaix A. General Framework about Defect Creation at the Si/SiO2 Interface // J. Appl. Phys.2009. V. 105. P. 114 513–1–114 513–12.

24. McMahon W., Matsuda K, Lee J., Hess K., Lyding J. The Effects of a Multiple Carrier Model of Interface States Generation of Lifetime Extraction for MOSFETs. in Proc. Int. Conf. Mod. Sim. Micro. 2002. V. 1. P. 576–579.

25. Fischetti M.V., Vandenberghe W.G. Advanced Physics of Electron Transport in Semiconductors and Nanostructures, New York, U.S.A.: Springer, 2016.

26. Reggiani S., Barone G., Poli S., Gnani E., Gnudi A., Baccarani G., Chuang M.Y., Tian W., Wise R. TCAD simulation of hot-carrier and thermal degradation in STI–LDMOS transistors // IEEE Trans. Electron Devices. 2013. V. 60. № 2. P. 691–698.

Comments

No posts found

Write a review
Translate