Везде
Investigation of ways to synthesize concurrent error-detection circuits based on boolean signals correction using uniform separable codes
Table of contents
Annotation Estimate Publication content
References Comments
Share
QR
Metrics
Investigation of ways to synthesize concurrent error-detection circuits based on boolean signals correction using uniform separable codes
Annotation
PII
S0544126924050079-1
Publication type
Article
Status
Published
Authors
D. V. Efanov 
Affiliation:
Peter the Great Saint Petersburg Polytechnic University
Russian University of Transport
Tashkent State Transport University
«Transport and Construction Safety» LLC
E. I. Yelina
Affiliation: Peter the Great Saint Petersburg Polytechnic University
Edition
Volume 53 Issue number 5
Pages
413-426
Abstract
The features of the synthesis of concurrent error-detection circuit based on the Boolean signals correction using uniform separable codes are investigated. Three types of structures are considered: type I – structure with correction of part of the signals from the outputs of the diagnostic object forming the check symbols of a given code in the concurrent error-detection circuit; type II – structure with correction of part of the signals from the outputs of the diagnostic object forming the data symbols of a given code in the concurrent error-detection circuit; type III – structure with signal correction from all outputs of the diagnostic object. For structures of all types, formulas are given for determining the number of ways to synthesize concurrent error-detection circuit based on the Boolean signals correction using a given code. New properties of structures have been established that characterize the features of the growth in the number of methods for synthesizing concurrent error-detection circuit with an increase in the number of outputs forming data and check symbols. Patterns have been found that allow in practice to estimate the number of ways to synthesize concurrent error-detection circuit based on the Boolean signals correction using uniform separable codes in order to select the best one according to specified criteria. Examples are given to demonstrate the effectiveness of using the found patterns.
Keywords
самопроверяемые цифровые устройства логическая коррекция сигналов равномерные разделимые коды в задачах обнаружения неисправностей синтез схем встроенного контроля
Received
23.02.2025
Number of purchasers
0
Views
21
Readers community rating
0.0 (0 votes)
Cite   Download pdf

References

1. Согомонян Е.С., Слабаков Е.В. Самопроверяемые устройства и отказоустойчивые системы. М.: Радио и связь, 1989, 208 с.

2. Mikoni S. Top Level Diagnostic Models of Complex Objects // Lecture Notes in Networks and Systems. – 2022. – Vol. 442. – Pp. 238–249. DOI: 10.1007/978–3–030–98832–6_21.

3. Drozd A., Kharchenko V., Antoshchuk S., Sulima J., Drozd M. Checkability of the Digital Components in Safety-Critical Systems: Problems and Solutions // Proceedings of 9th IEEE East-West Design & Test Symposium (EWDTS’2011), Sevastopol, Ukraine, 2011, pp. 411–416. doi: 10.1109/EWDTS.2011.6116606.

4. Drozd O., Perebeinos I., Martynyuk O., Zashcholkin K., Ivanova O., Drozd M. Hidden Fault Analysis of FPGA Projects for Critical Applications // Proceedings of the IEEE International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering (TCSET), 25–29 February 2020, Lviv-Slavsko, Ukraine, paper 142. doi: 10.1109/TCSET49122.2020.235591.

5. Göessel M., Ocheretny V., Sogomonyan E., Marienfeld D. New Methods of Concurrent Checking: Edition 1. – Dordrecht: Springer Science+Business Media B. V., 2008, 184 p.

6. Borecký J., Kohlík M., Kubátová H. Parity Driven Reconfigurable Duplex System // Microprocessors and Microsystems. – 2017. – Vol. 52. – Pp. 251–260. doi: 10.1016/j.micpro.2017.06.015.

7. Tshagharyan G., Harutyunyan G., Shoukourian S., Zorian Y. Experimental Study on Hamming and Hsiao Codes in the Context of Embedded Applications // Proceedings of 15th IEEE East-West Design & Test Symposium (EWDTS’2017), Novi Sad, Serbia, September 29 – October 2, 2017, pp. 25–28. doi: 10.1109/EWDTS.2017.8110065.

8. Сапожников В.В., Сапожников Вл.В., Ефанов Д.В. Коды с суммированием для систем технического диагностирования. Том 1: Классические коды Бергера и их модификации. – М.: Наука, 2020, 383 с.

9. Сапожников В.В., Сапожников Вл.В., Ефанов Д.В. Коды с суммированием для систем технического диагностирования. Том 2: Взвешенные коды с суммированием. – М.: Наука, 2021, 455 с.

10. Stempkovsky A.L., Zhukova T.D., Telpukhov D.V., Gurov S.I. CICADA: A New Tool to Design Circuits with Correction and Detection Abilities // International Siberian Conference on Control and Communications (SIBCON), 13–15 May 2021, Kazan, Russia pp. 1–5. doi: 10.1109/SIBCON50419.2021.9438900.

11. Nicolaidis M. On-Line Testing for VLSI: State of the Art and Trends // Integration, the VLSI Journal, 1998, Vol. 26, Issues 1–2, pp. 197–209. doi: 10.1016/S0167–9260(98)00028–5.

12. Mitra S., McCluskey E.J. Which Concurrent Error Detection Scheme to Сhoose? // Proceedings of International Test Conference, 2000, USA, Atlantic City, NJ, 03–05 October 2000, pp. 985–994. doi: 10.1109/TEST.2000.894311.

13. Ефанов Д.В., Сапожников В.В., Сапожников Вл.В. О свойствах кода с суммированием в схемах функционального контроля // Автоматика и телемеханика. – 2010. – № 6. – С. 155–162.

14. Гессель М., Морозов А.В., Сапожников Вл.В., Сапожников Вл.В. Контроль комбинационных схем методом логического дополнения // Автоматика и телемеханика. – 2005. – № 8. – С. 161–172.

15. Гессель М., Морозов А.В., Сапожников Вл.В., Сапожников Вл.В. Логическое дополнение – новый метод контроля комбинационных схем // Автоматика и телемеханика. – 2003. – № 1. – С. 167–176.

16. Sen S.K. A Self-Checking Circuit for Concurrent Checking by 1-out-of-4 code with Design Optimization using Constraint Don’t Cares // National Conference on Emerging trends and advances in Electrical Engineering and Renewable Energy (NCEEERE2010), Sikkim Manipal Institute of Technology, Sikkim, held during 22–24 December, 2010.

17. Das D.K., Roy S.S., Dmitiriev A., Morozov A., Gössel M. Constraint Don’t Cares for Optimizing Designs for Concurrent Checking by 1-out-of-3 Codes // Proceedings of the 10th International Workshops on Boolean Problems, Freiberg, Germany, September, 2012, pp. 33–40.

18. Пивоваров Д.В. Построение систем функционального контроля многовыходных комбинационных схем методом логического дополнения по равновесным кодам // Автоматика на транспорте. – 2018. – Том 4. – № 1. – С. 131–149.

19. Morozov M., Saposhnikov V. V., Saposhnikov Vl.V., Goessel M. New Self-Checking Circuits by Use of Berger-codes // Proceedings of 6th IEEE International On-Line Testing Workshop, Palma De Mallorca, Spain, 3–5 July 2000, pp. 171–176.

20. Efanov D.V., Sapozhnikov V.V., Sapozhnikov Vl.V. The Self-Checking Concurrent Error-Detection Systems Synthesis Based on the Boolean Complement to the Bose-Lin Codes with the Modulo Value M=4 // Electronic Modeling. – 2021. – Vol. 43. – Issue 1. – Pp. 28–45. DOI: 10.15407/emodel.43.01.028.

21. Ефанов Д.В., Зуева М.В. Свойства кодов Сяо в системах технического диагностирования дискретных устройств // Программная инженерия. – 2023. – Т. 14. – № 7. – С. 339–349. DOI: 10.17587/prin.14.339–349.

22. Saposhnikov Vl.V., Dmitriev A., Goessel M., Saposhnikov V.V. Self-Dual Parity Checking – a New Method for on Line Testing // Proceedings of 14th IEEE VLSI Test Symposium, USA, Princeton, 1996, pp. 162–168.

23. Гессель М., Дмитриев А.В., Сапожников Вл.В., Сапожников В.В. Обнаружение неисправностей в комбинационных схемах с помощью самодвойственного контроля // Автоматика и телемеханика. – 2000. – № 7. – С. 140–149.

24. Efanov D., Sapozhnikov V., Sapozhnikov Vl., Osadchy G., Pivovarov D. Self-Dual Complement Method up to Constant-Weight Codes for Arrangement of Combinational Logical Circuits Concurrent Error-Detection Systems // Proceedings of 17th IEEE East-West Design & Test Symposium (EWDTS’2019), Batumi, Georgia, September 13–16, 2019, pp. 136–143. doi: 10.1109/EWDTS.2019.8884398.

25. Efanov D.V., Pivovarov D.V. The Hybrid Structure of a Self-Dual Built-In Control Circuit for Combinational Devices with Pre-Compression of Signals and Checking of Calculations by Two Diagnostic Parameters // Proceedings of 19th IEEE East-West Design & Test Symposium (EWDTS’2021), Batumi, Georgia, September 10–13, 2021, pp. 200–206. doi: 10.1109/EWDTS52692.2021.9581019.

26. Пашуков А.В. Применение взвешенных кодов с суммированием при синтезе схем встроенного контроля по методу логического дополнения // Автоматика на транспорте. – 2022. – Том 8. – № 1. – С. 101–114. DOI: 10.20295/2412–9186–2022–8–01–101–114.

27. Ефанов Д.В., Елина Е.И. Исследование алгоритмов синтеза самопроверяемых цифровых устройств на основе логической коррекции сигналов с применением взвешенных кодов Боуза – Лина // Автоматика на транспорте. – 2024. – Том 10. – № 1. – С. 74–99. DOI: 10.20296/2412–9186–2024–10–01–74–99.

28. Ефанов Д.В. Синтез самопроверяемых комбинационных устройств на основе метода логической коррекции сигналов с применением кодов Боуза – Лина // Информационные технологии. – 2023. – Том 29. – № 10. – С. 503–511. DOI: 10.17587/it.29.503–511.

29. Efanov D.V., Yelina Y.I. Synthesis of Concurrent Error-Detection Circuits Based on Boolean Signals Correction Using Modular Weight-Based Sum Codes // Proceedings of the 2024 Conference of Young Researchers in Electrical and Electronic Engineering (EICon), 29–30 January 2024, St. Petersburg, Russia, pp. 350–355. doi: 10.1109/ElCon61730.2024.10468328.

30. Сапожников В. В., Сапожников Вл.В., Ефанов Д. В. Коды Хэмминга в системах функционального контроля логических устройств: монография. – СПб.: Наука, 2018, 151 с.

Comments

No posts found

Write a review
Translate