Simulation of silicon conical field effect GAA nanotransistors with stack SiO2/HfO2 dielectric of gate
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Simulation of silicon conical field effect GAA nanotransistors with stack SiO2/HfO2 dielectric of gate
Annotation
PII
S0544126924030044-1
Publication type
Article
Status
Published
Authors
N. V. Masalsky 
Affiliation: Federal Research Center Scientific Research Institute for System Research, Russian Academy of Sciences Academy
Pages
222-231
Abstract
The issues of modeling the electrophysical characteristics of a silicon conical field effect GAA nanotransistor are discussed. An analytical model of the drain current of a transistor with a fully enclosing conical gate with a stack sub-gate oxide SiO2/HfO2 has been developed, taking into account the effect of the charge of the interphase trap at the Si/SiO2 interface. To simulate the potential distribution in a conical working area under the condition of constant trap density, an analytical solution of the Poisson equation was obtained using the method of parabolic approximation in a cylindrical coordinate system with appropriate boundary conditions. The potential model was used to develop an expression for the GAA drain current of a nanotransistor with a stack gate oxide. The key electrophysical characteristics are numerically investigated depending on the density of traps and the thicknesses of SiO2 and HfO2 layers.
Keywords
кремневая нанотранзисторная архитектура полностью охватывающий затвор коническая рабочая область подзатворный стековый диэлектрик с высоким k моделирование
Acknowledgment
The publication was carried out within the framework of research at the Federal State University of the Federal Research Center of the Russian Academy of Sciences on the topic FNEF-2024-0003 “Methods for developing hardware and software platforms based on secure and fault-resistant systems on a chip and artificial intelligence and signal processing coprocessors”.
Received
27.10.2024
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References

1. Usha C., Vimala P. Analytical drain current model for fully depleted surrounding gate TFET // J. Nano Res. 2018. V. 55. P. 75—81.

2. Nanoelectronics: Devices, Circuits and Systems // Editor by Brajesh Kumar Kaushik. Elsevier. 2018.

3. Tomar G., Barwari A. Fundamental of electronic devices and circuits // Springer. 2019. 224 р.

4. Colinge J.P. FinFETs and Other Multi-Gate Transistor // NewYork: Springer-Verlag. 2008. 339 р.

5. Ferain I., Colinge C.A., Colinge J. Multigate transistors as the future of classical metal—oxide—semiconductor field-effect transistors // Nature. 2011. V. 479. P. 310—316.

6. International Technology Roadmap for Semiconductors (ITRS) Interconnect, 2020 Edition. [Online] Available: https://irds.ieee.org/editions/2020 (data access 12.12.2022).

7. Kumar S., Goel E., Singh K., Singh B., Kumar M., Jit S. A compact 2D analytical model for electrical characteristics of double-gate tunnel field-effect transistors with a SiO2/high-k stacked gate-oxide structure // IEEE Trans. Electron Devices. 2016. V. 63. P. 3291—3330.

8. Масальский Н.В. Моделирование кремниевых цилиндрических с полностью охватывающим затвором КМОП нанотранзисторов с переменным радиусом // Микроэлектроника. 2022. T. 51. C. 220—225.

9. Koswatta S.O., Lundstrom M.S., Nikonov D.E. Performance comparison between pin tunneling transistors and conventional MOSFETs // IEEE Trans. Electron. Dev. 2009. V. 56. P. 456—463.

10. Yu Y.S., Cho N., Hwang S.W., Ahn D. Analytical threshold voltage model including effective conducting path effect (ECPE) for surrounding-gate MOSFETs (SGMOSFETs) with localized charges // IEEE Trans. Electron. Dev. 2010. V. 57. P. 3176—3180.

11. Abdi D.B., Kumar M.J. 2-D threshold voltage model for the double-gate pnpn TFET with localized charges // IEEE Trans. Electron. Dev. 2016. V. 63. P. 3663—3668.

12. Grasser T. (ed.). Bias Temperature Instability for Devices and Circuits // Springer Science + Business Media. New York, 2014.

13. Sahay S., Kumar M. Junctionless Field-Effect Transistors: Design, Modeling, and Simulation // Wiley-IEEE Press. 2019.

14. Lundstrom M., Guo J. Nanoscale Transistors: Device Physics, Modeling and Simulation // Springer: New York, 2006.

15. Schwierz F., Wong H., Liou J.J. Nanometer CMOS. Pan Stanford Publishing // Singapore. 2010.

16. Sano N. Physical issues in device modeling: Length-scale, disorder, and phase interference // Iin 2017 International Conference on Simulation of Semiconductor Processes and Devices, Sept. 2017. Р. 1—4.

17. Fischetti M.V., Vandenberghe W.G. Advanced Physics of Electron Transport in Semiconductors and Nanostructures. New York, U.S.A.: Springer, 2016.

18. Reggiani S., Barone G., Poli S., Gnani E., Gnudi A., Baccarani G., Chuang M.-Y., Tian W., Wise R. TCAD simulation of hot-carrier and thermal degradation in STI-LDMOS transistors // IEEE Trans. Electron Devices. 2013. V. 60. P. 691—698.

19. Young K. K. Analysis of conduction in fully depleted SOI MOSFETs // IEEE Trans. Electron Devices. 1989. V. 36. P. 504—506.

20. Bardon M.G., Neves H.P., Puers R., Van Hoof C. Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions // IEEE Trans. Electron Devices. 2010. V. 57. P. 827—834.

21. Chiang T.K., Chen M.L. A new analytical threshold voltage model for symmetrical double-gate MOSFETs with high-k gate dielectrics // Solid-State Electron. 2007. V. 51. P. 387—393.

22. He J., Chan M., Zhang X., Wang Y. A carrier-based analytic model for the undoped (lightly doped) cylindrical surrounding-gate MOSFETs // Solid State Electron. 2006. V. 50. P. 416—421.

23. Sze S.M. Physics of Semiconductor Device. 2nd edn. John Wiley & Sons Inc.: Hoboken, New Jersey.

24. Karthigai Pandian M., Balamurugan N.B. Analytical threshold voltage modeling of surrounding gate silicon nanowire transistors with different geometries // J. Electric Eng. Technol. 2014. V. 9. P. 742—751.

25. Chiang T-K. A new quasi-3-D compact threshold voltage model for Pi-gate MOSFETs with the interface trapped charges // IEEE Transactions on Nanotechnology. 2015. V. 14. P. 555—560.

26. Auth C.P., Plummer J.D. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFETs // IEEE Trans. on Electron Devices. 1997. V. 18. P. 74—76.

27. Масальский Н.В. Моделирование характеристик КМОП нанотранзистора с полностью охватывающим затвором и неравномерно легированной рабочей областью // Микроэлектроника. 2019. T. 48. C. 436—444.

28. Масальский Н.В. Моделирование ВАХ ультратонких КНИ КМОП нанотранзисторов с полностью охватывающим затвором // Микроэлектроника. 2021. T. 50. C. 436—444.

29. Madan J., Chaujar R. Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance // Superlattices Microstruct. 2017. V. 102. P. 17—26.

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